Nickel Cadmium and Nickel Metal Hydride batteries require precise charge termination control to maximize cell capacity and operating time while preventing overcharging. Overcharging can result in a reduction of battery life as well as physical harm to the end user. Since most portable applications require the batteries to be charged rapidly, a primary and usually a secondary or redundant charge sensing technique is employed into the charging system. It is also desirable to disable rapid charging if the battery voltage or temperature is either too high or too low. In order to address these issues, an economical and flexible fast charge controller was developed. The MC33340 and MC33342 contains many of the building blocks and protection features that are employed in modern high performance battery charger controllers that are specifically designed for Nickel Cadmium and Nickel Metal Hydride batteries. The device is designed to interface with either primary or secondary side regulators for easy implementation of a complete charging system. A representative block diagram in a typical charging application is shown in Figure 1 .

The battery voltage is monitored by the V_sen input that internally connects to a voltage to frequency converter and counter for detection of a negative slope in battery voltage. A timer with three programming inputs is available to provide backup charge termination. Alternatively, these inputs can be used to monitor the battery pack temperature and to set the over and under temperature limits also for backup charge termination.

Two active low open collector outputs are provided to interface this controller with the external charging circuit. The first output furnishes a gating pulse that momentarily interrupts the charge current. This allows an accurate method of sampling the battery voltage by eliminating voltage drops that are associated with high charge currents and wiring resistances. Also, any noise voltages generated by the charging circuitry are eliminated. The second output is designed to switch the charging source between fast and trickle modes based upon the results of voltage, time, or temperature. These outputs normally connect directly to a linear or switching regulator control circuit in non–isolated primary or secondary side applications. Both outputs can be used to drive optoisolators in primary side applications that require galvanic isolation. Figure 2 shows the typical charge characteristics for NiCd and NiMh batteries.

Figure 1. MC33340 and MC33342 Typical Battery Charging Application

Figure 2. Typical Charge Characteristics for NiCd and NiMh Batteries

The MC33340 and MC33342 starts up in the fast charge mode when power is applied to V_CC. A change to the trickle mode can occur as a result of three possible conditions. The first is if the Vsen input voltage is above 2.0 V or below 1.0 V. Above 2.0 V indicates that the battery pack is open or disconnected, while below 1.0 V indicates the possibility of a shorted or defective cell. The second condition is when the MC33340 and MC33342 detects a fully charged battery by measuring a negative slope in battery voltage. The MC33340 and MC33342 recognize a negative voltage slope after the preset holdoff time (thold) has elapsed during a fast charge cycle. This indicates that the battery pack is fully charged. The third condition is either due to the battery pack being out of a programmed temperature range, or that the preset timer period has been exceeded.

There are three conditions that will cause the controller to return from trickle to fast charge mode. The first is if the V_sen input voltage moved to within the 1.0 to 2.0 V range from initially being either too high or too low. The second is if the battery pack temperature moved to within the programmed temperature range, but only from initially being too cold. Third is by cycling V_CC off and then back on causing the internal logic to reset. A concise description of the major circuit blocks is given below

Negative Slope Voltage Detection

A representative block diagram of the negative slope voltage detector is shown in Figure 3 . It includes a Synchronous Voltage to Frequency Converter, a Sample Timer, and a Ratchet Counter. The V_sen pin is the input for the Voltage to Frequency Converter (VFC), and it connects to the rechargeable battery pack terminals through a resistive voltage divider. The input has an impedance of approximately 6.0 MΩ and a maximum voltage range of –1.0 V to V_CC + 0.6 V or 0 V to 10 V, whichever is lower. The 10 V upper limit is set by an internal zener clamp that provides protection in the event of an electrostatic discharge. The VFC is a charge–balanced synchronous type which generates output pulses at a rate of F_V = V_sen (24 kHz).

The Sample Timer circuit provides a 95 kHz system clock signal (SCK) to the VFC. This signal synchronizes the F_V output to the other Sample Timer outputs used within the detector. At 1.38 second intervals the V_sen Gate output goes low for a 33 ms period. This output is used to momentarily interrupt the external charging power source so that a precise voltage measurement can be taken. As the V_sen Gate goes low, the internal Preset control line is driven high for 11 ms. During this time, the battery voltage at the Vsen input is allowed to stabilize and the previous F_V count is preloaded. At the Preset high–to–low transition, the Convert line goes high for 22 ms. This gates the F_V pulses into the ratchet counter for a comparison to the preloaded count. Since the Convert time is derived from the same clock that controls the VFC, the number of F_V pulses is independent of the clock frequency. If the new sample has more counts than were preloaded, it becomes the new peak count and the cycle is repeated 1.38 seconds later. If the new sample has two fewer counts, a less than peak voltage event has occurred, and a register is initialized. If two successive less than peak voltage events occur, the –ΔV ‘AND’ gate output goes high and the Fast/Trickle output is latched in a low state, signifying that the battery pack has reached full charge status.

Negative slope voltage detection starts after 60 ms have elapsed in the fast charge mode. This does not affect the Fast/Trickle output until the holdoff time (thold) has elapsed during the fast charge mode. Two scenarios then exist. Trickle mode holdoff is implemented to ignore any initial drop in voltage that may occur when charging batteries that have been stored for an extended time period. If the negative slope voltage detector senses that initial drop during the holdoff time, and the input voltage rises as the battery charges, the Fast/Trickle output will remain open. However, if the negative slope voltage detector senses a negative drop in voltage during the holdoff time and the input voltage never rises above that last detected level, the Fast/Trickle output will latch into a low state. The negative slope voltage detector has a maximum resolution of 2.0 V divided by 1023, or 1.955 mV per count with an uncertainty of ±1.0 count. This yields a detection range of 1.955 mV to 5.865 mV. In order to obtain maximum sensing accuracy, the R₂/R₁ voltage divider must be adjusted so that the Vsen input voltage is slightly less than 2.0 V when the battery pack is fully charged. Voltage variations due to temperature and cell manufacturing must be considered.

Figure 3. Negative Slope Voltage Detector

Fast Charge Timer

A programmable backup charge timer is available for fast charge termination. The timer is activated by the Time/Temp Select comparator, and is programmed from the t₁/T_ref High, t₂/T_sen, and t₃/T_ref Low inputs. If one or more of these inputs is allowed to go above V_CC – 0.7 V or is left open, the comparator output will switch high, indicating that the timer feature is desired. The three inputs allow one of seven possible fast charge time limits to be selected. The programmable time limits, rounded to the nearest whole minute, are shown in Figure 4 .

Over/Under Temperature Detection

A backup over/under temperature detector is available and can be used in place of the timer for fast charge termination. The timer is disabled by the Time/Temp Select comparator when each of the three programming inputs are held below V_CC – 0.7 V.

Temperature sensing is accomplished by placing a negative temperature coefficient (NTC) thermistor in thermal contact with the battery pack. The thermistor connects to the t₂/T_sen input which has a 30 mA current source pull–up for developing a temperature dependent voltage. The temperature limits are set by a resistor that connects from the t₁/T_ref High and the t₃/T_ref Low inputs to ground. Since all three inputs contain matched 30 mA current source pull–ups, the required programming resistor values are identical to that of the thermistor at the desired over and under trip temperature. The temperature window detector is composed of two comparators with a common input that connects to the t₂/T_sen input.

The lower comparator senses the presence of an under temperature condition. When the lower temperature limit is exceeded, the charger is switched to the trickle mode. The comparator has 44 mV of hysteresis to prevent erratic switching between the fast and trickle modes as the lower temperature limit is crossed. The amount of temperature rise to overcome the hysteresis is determined by the thermistor’s rate of resistance change or sensitivity at the under temperature trip point. The required resistance change is:

Figure 4. Fast Charge Backup Termination Time/Temperature Limit

The resistance change approximates a thermal hysteresis of 2°C with a 10 kΩ thermistor operating at 0°C. The under temperature fast charge inhibit feature can be disabled by biasing the t₃/T_ref Low input to a voltage that is greater than that present at t₂/T_sen, and less than V_CC – 0.7 V. Under extremely cold conditions, it is possible that the thermistor resistance can become too high, allowing the t2/Tsen input to go above V_CC – 0.7 V, and activate the timer. This condition can be prevented by placing a resistor in parallel with the thermistor. Note that the time/temperature threshold of V_CC – 0.7 V is a typical value at room temperature. 

The upper comparator senses the presence of an over temperature condition. When the upper temperature limit is exceeded, the comparator output sets the Over Temperature Latch and the charger is switched to trickle mode. Once the latch is set, the charger cannot be returned to fast charge, even after the temperature falls below the limit. This feature prevents the battery pack from being continuously temperature cycled and overcharged. The latch can be reset by removing and reconnecting the battery pack or by cycling the power supply voltage.

If the charger does not require either the time or temperature backup features, they can both be easily disabled. This is accomplished by biasing the t₃/T_ref Low input to a voltage greater than t₂/T_sen, and by grounding the t₁/T_ref High input. Under these conditions, the Time/Temp Select comparator output is low, indicating that the  temperature mode is selected, and that the t₂/T_sen input is biased within the limits of an artificial temperature window.

Charging of battery packs that are used in portable power tool applications typically use temperature as the only means for fast charge termination. The MC33340 and MC33342 can be configured in this manner by constantly resetting the –ΔV detection logic. This is accomplished by biasing the Vsen input to 1.5 V from a two resistor divider that is connected between the positive battery pack terminal and ground. The V_sen Gate output is also connected to the Vsen input. Now, each time that the Sample Timer causes the V_sen output to go low, the Vsen input will be pulled below the undervoltage threshold of 1.0 V. This causes a reset of the –ΔV logic every 1.38 seconds, thus disabling detection.

Figure 5. Controller Operating Mode Table

Operating Logic

The order of events in the charging process is controlled by the logic circuitry. Each event is dependent upon the input conditions and the chosen method of charge termination. A table summary containing all of the possible operating modes is shown in Figure 5 .

Testing

Under normal operating conditions, it would take 283 minutes to verify the operation of the 34 stage ripple counter used in the timer. In order to significantly reduce the test time, three digital switches were added to the circuitry and are used to bypass selected divider stages. Entering each of the test modes without requiring additional package pins or affecting normal device operation proved to be challenging. Refer to the timer functional block diagram in Figure 6 .

Switch 1 bypasses 19 divider stages to provide a 524,288 times speedup of the clock. This switch is enabled when the V_sen input falls below 1.0 V. Verification of the programmed fast charge time limit is accomplished by measuring the propagation delay from when the V_sen input falls below 1.0 V, to when the F/T output changes from a high–to–low state. The 71, 106, 141, 177, 212, 247 and 283 will now correspond
to 8.1, 12.1, 16.2, 20.2, 24.3, 28.3 and 32.3 ms delays. It is possible to enter this test mode during operation if the equivalent battery pack voltage was to fall below 1.0 V. This will not present a problem since the device would normally switch from fast to trickle mode under these conditions, and the relatively short variable time delay would be transparent to the user.

Switch 2 bypasses 11 divider stages to provide a 2048 times speedup of the clock. This switch is necessary for testing the 19 stages that were bypassed when switch 1 was enabled. Switch 2 is enabled when the Vsen input falls below 1.0 V and the t₁/T_ref High input is biased at –100 mV. Verification of the 19 stages is accomplished by measuring a nominal propagation delay of 338.8 ms from when the Vsen input falls below 1.0 V, to when the F/T output changes from a high–to–low state.

Switch 3 is a dual switch consisting of sections “A” and “B”. Section “A” bypasses 5 divider stages to provide a 32 times speedup of the V_sen gate signal that is used in sampling the battery voltage. This speedup allows faster test verification of two successive –ΔV events. Section “B” bypasses 11 divider stages to provide a 2048 speedup of the trickle mode holdoff timer. Switches 3A and 3B are both activated when the t₁/T_ref High input is biased at –100 mV with respect to Pin 4.

Figure 6. MC33340 and MC33342 Timer Functional Block Diagram

Figure 7. MC33340 and MC33342 Line Isolated Linear Regulator Charger

This application combines the MC33340 and MC33342 with an adjustable three terminal regulator to form an isolated secondary side battery charger. Regulator IC₂ operates as a constant current source with R₇ setting the fast charge level. The trickle charge level is set by R₅. The R₂/R₁ divider should be adjusted so that the V_sen input is less than 2.0 V when the batteries are fully charged. The printed circuit board shown below will accept the several TO–220 style heatsinks for IC2

Figure 8. MC33340 and MC33342 Printed Circuit Board Component and Layout