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555 Timer Family
Written by Jimmy   
Thursday, 26 July 2007

The SE555 - NE555 - LM555 is a highly stable device for generating accurate time delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output circuit can source or sink up to 200 mA ordrive TTL circuits.

Pin-for-pin compatible with 555 series of timers
 Manufacturer Type Number
 ECG Philips
 ECG955M
 Exar XR-555
 Fairchild NE555
 Harris HA555
 Intersil SE555 / NE555
 Lithic Systems
 LC555
 Maxim ICM7555
 Motorola MC1455 / MC1555
 National LM1455 / LM555 / LMC555
 NTE Sylvania
 NTE955
 Raytheon RM555 / RC555
 RCA CA555 / CA555C
 Sanyo LC7555
 Texas Instruments
 SN52555 / SN72555

MONOSTABLE OPERATION

In this mode of operation, the timer functions as a one-shot ( Figure 1 ). The external capacitor is initially held discharged by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 VCC to pin 2, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high.

The voltage across the capacitor then increases exponentially for a period of t = 1.1 RA C, at the end of which time the voltage equals 2/3 VCC. The comparator then resets the flip-flop which in turn discharges the capacitor and drives the output to its low state. Figure 2 shows the waveforms generated in this mode of operation. Since the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing internal is independent of supply.

 SE555 - NE555 - LM555 Monostable
Figure 1. LM555 Monostable
 SE555 - NE555 - LM555 Monostable Waveforms
Figure 2. LM555 Monostable Waveforms

During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10 ms before the end of the timing interval. However the circuit can  be reset during this time by the application of a negative pulse to the reset terminal (pin 4). The output will then remain in the low state until a trigger pulse is again applied. When the reset function is not in use, it is recommended that it be connected to VCC to avoid any possibility of false triggering.

Figure 3 is a nomograph for easy determination of R, C values for various time delays.

NOTE: In monostable operation, the trigger should be driven high before the end of timing cycle.

SE555 - NE555 - LM555 Time Delay
Figure 3. LM555 Time Delay

ASTABLE OPERATION

If the circuit is connected as shown in Figure 4 (pins 2 and 6 connected) it will trigger itself and free run as a multivibrator. The external capacitor charges through RA a RB and discharges through RB. Thus the duty cycle may be precisely set by the ratio of these two resistors. In this mode of operation, the capacitor charges and discharges between 1/3 VCC and 2/3 VCC. As in the triggered mode, the charge and discharge times, and therefore the frequency are independent of the supply voltage.

Figure 5 shows the waveforms generated in this mode of operation.

 SE555 - NE555 - LM555 Astable
Figure 4. LM555 Astable
 SE555 - NE555 - LM555 Astable Waveforms
Figure 5. LM555 Astable Waveforms

The charge time (output high) is given by:
t1 = 0.693 (RA + RB) C
And the discharge time (output low) by:
t2 = 0.693 (RB) C
Thus the total period is:
T = t1 + t2 = 0.693 (RA +2RB) C
The frequency of oscillation is:
f  = 1/T = 1.44/((RA +2RB) C)
The duty cycle is: D = RB/(RA +2RB)

Figure 6 may be used for quick determination of these RC values.

SE555 - NE555 - LM555 Free Running Frequency
Figure 6. LM555 Free Running Frequency

FREQUENCY DIVIDER

The monostable circuit of Figure 1 can be used as a frequency divider by adjusting the length of the timing cycle. Figure 7 shows the waveforms generated in a divide by three circuit.

SE555 - NE555 - LM555 Frequency Divider
Figure 7. LM555 Frequency Divider(divide by 3)

PULSE WIDTH MODULATOR (PWM)

When the timer is connected in the monostable mode and triggered with a continuous pulse train, the output pulse width can be modulated by a signal applied to pin 5. Figure 8 shows the circuit, and in Figure 9 are some waveform examples.

 SE555 - NE555 - LM555 Pulse Width Modulator
Figure 8. LM555 Pulse Width Modulator
 SE555 - NE555 - LM555 Pulse Width Modulator Waveform
Figure 9. LM555 Pulse Width Modulator Waveforms

PULSE POSITION MODULATOR

This application uses the timer connected for astable operation, as in Figure 10 , with a modulating signal again applied to the control voltage terminal. The pulse position varies with the modulating signal, since the threshold voltage and hence the time delay is varied. Figure 11 shows the waveforms generated for a triangle wave modulation signal.

 SE555 - NE555 - LM555 Pulse Position Modulator
Figure 10. LM555 Pulse Position Modulator
 SE555 - NE555 - LM555 Pulse Position Modulator Waveforms
Figure 11. LM555 Pulse Position Modulator Waveforms

LINEAR RAMP

When the pullup resistor, RA, in the monostable circuit is replaced by a constant current source, a linear ramp is generated. Figure 12 shows a circuit configuration that will perform this function.

The time interval is given by:

LM555 Linear Ramp Formula 

 SE555 - NE555 - LM555 Linear Ramp
Figure 12. LM555 Linear Ramp
SE555 - NE555 - LM555 Linear Ramp Waveforms
Figure 13. LM555 Linear Ramp Waveforms

50% DUTY CYCLE OSCILLATOR

For a 50% duty cycle, the resistors RA and RB may be connected as in Figure 14 . The time period for the output high is the same as previous, t1 = 0.693 RA C. For the output low it is t2 = LM555 CYCLE OSCILLATOR Formula

Thus the frequency of oscillation is f = 1/(t1 + t2)

SE555 - NE555 - LM555 50 % Duty Cycle Oscillator
Figure 14. LM555 50 % Duty Cycle Oscillator

 

Note that this circuit will not oscillate if RB is greater than 1/2 RA because the junction of RA and RB cannot bring pin 2 down to 1/3 VCC and trigger the lower comparator.

ADDITIONAL INFORMATION

Adequate power supply bypassing is necessary to protect associated circuitry. Minimum recommended is 0.1 μF in parallel with 1 μF electrolytic. Lower comparator storage time can be as long as 10 ms when pin 2 is driven fully to ground for triggering. This limits the monostable pulse width to 10 ms minimum. Delay time reset to output is 0.47 ms typical. Minimum reset pulse width must be 0.3 ms, typical. Pin 7 current switches within 30 ns of the output (pin 3) voltage.

Last Updated ( Thursday, 26 July 2007 )
 
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